Linear Decision Diagrams

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Linear Decision Diagrams
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• Svetlana Yanushkevich,Piotr Dziurzanski

Faculty of Computer Science and Information
Systems, Technical University of Szczecin,
Poland yanushkevich_at_wi.ps.pl
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Idea of approach
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Logic Synthesis
Model a set of Linear Decision Diagrams (LDDs)
Fabrication of planar model
Physical Level
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Related research
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• V. Feinberg et al., VLSI Planarization Methods,
  Models, Implementation, 1997, Kluwer Academic
  Publishers
• M. Nakajima, M. Kameyama, Design of Highly
  Parallel Linear Digital System for ULSI
  Processors, IEICE Trans., 1993 V.7, No.E76-C,
  1119-1125

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Why planarization is important ?
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• In deep-submicron VLSI the gate delays have
  become less significant than the routing delays
  in interconnects
• It is expected that interconnect contributes
  up to about 70 in advanced technology

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Definition The Linear Arithmetic Expression
(LAR) of a multivalued function f of n variables
x1, ..., xn is the expression
where di are integers. Remark Binary case of
LAR was studied by Kamamiya in 1951 (Bull. of
E.T.L., 1951, Vol. 15, No. 8, 188-197)
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Problem Find coefficients di in the LAR of
a multiple-valued function f
Remark Even primitive 2-input ternary gates
MAX, MIN, TSUM, TPROD, MODPROD do not derive
LARs.
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Method
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We utilized the method of pseudo-variables
proposed by V. Antonenko, A. Ivanov, V.
Shmerko, Linear Arithmetical Forms of k-valued
Logic Functions and their Realization on Systolic
Arrays, Automation and Remote Control (USA),
vol. 56, no. 3, Pt. 2, 1995, pp. 419-432
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Algorithm
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• Divide a truth vector into parts
• Build truth table X
• Find the coefficients of LARs

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Truth matrix of 2-input ternary MAX gate
f
x1
MAX
x2
weight
30
31
32
index of column
0
1
2
ù
é
ù
é
21
0
1
2
0
ú
ê
ú
ê



22
1
1
2




X
X
X
X
1
ú
ê
ú
ê
0
1
2
ú
ê
ú
ê
26
2
2
2
2
û
ë
û
ë
index of row
ternary vector
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Matrix of LAR coefficients
0 0
0 1
pseudo-variables
1 0
Matrix formed from orthogonal transformation
matrix.
The model of MAX gate is
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Strategy to design LDD model

• Represent an initial MVL circuit by LAR,
  level by level,
• For each LAR build an LDD,
• Calculate circuit output
• based on a set of LDDs
• Related research T. Sasao, J. Butler, Planar
  decision diagrams for multiple-valued functions,
  Int. Journal on Multiple-Valued Logic, 1996,
  V. 1, 39-64

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The level of MVL circuit with 3-gates
x
1
y
MAX
x
1
2
x
MOD-SUM
y
3
x
2
4
x
5
y
MIN
x
3
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LARs for the gates
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LAR model of a circuit level
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Build LDD to represent LAR
Definition. LDD is a linear tree with nodes to
realize arithmetic positive Davio expansion
where and
Property. The factor (f1-f0) in the right branch
of LDD is always constant
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LDD library of 2-input ternary gates
f
f
f
x1
x1
x1
MIN
MOD-SUM
MAX
x2
x2
x2
pDA
pDA
pDA
0
0
0
21
5
-10
pDA
pDA
pDA
0
0
0
12
0
1
21
-14
21
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LDD model of the level of circuit
pDA
0
5
pDA
0
1
pDA
0
x
1
-270
y
MAX
pDA
x
1
0
2
x
-378
MOD-SUM
y
3
pDA
0
x
2
4
x
15309
pDA
5
y
MIN
0
x
3
6
588
8748
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Calculation of circuit output based on LDD model
LDDs are connected with mailboxes
pD
A
pD
o
x
0
A
o
y
i
0
i
di
dj
pD
A
0
o
x
i1
di1
d0
...
mailbox
mailbox
...
...
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Properties of LDD based model

• Planar by their nature
• Requires O(G.log(G)) of memory
• Requires O(L) of time
• MVL circuit with L levels is represented by a
  set of L LDDs

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Results on transformation of ISCAS85 benchmarks
to the LDD based model
Note binary gates are interpreted as ternary
gates
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Observation
1. Transformation of circuit data structure to
the LDD model is very fast 2. Memory
requirements, the number of nodes and the number
of LDDs satisfy the practical needs
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Memory requirements for LDD based model tested
with LGSYNTH93 (EDIF) and ISCAS85 benchmarks
Note binary gates are interpreted as ternary
gates
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Observation
LDD model requires less memory space compared
with EDIF and ISCAS85 formats. For instance, to
represent 32-bit adder C6288 by a set of LDDs we
need about ten times less memory.
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Conclusion
An arbitrary multiple-valued, multi-level
combinational circuit can be effectively
represented by a set of LDDs that are planar by
their nature
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Acknowledgment
We highly appreciate discussion and support
by Prof. V. Shmerko and Prof. G. Dueck.