TED

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TED

• Integrated tool set for electro-thermal
  evaluation of ICs

Pultronics Inc.
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Outline

• Introduction
• Pultronics approach
• Algorithm description
• Test results
• Conclusion

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Increasing heat flux

• Heat flux exceeding 10 W/cm2
• High temperatures
• Failure rate doubles approx. every 10oC

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Impact on expected performances

• Device mismatch
• thermal offset
• signal level mismatch
• decreased noise margin
• Thermally induced signal delay
• Reliability
• electro-migration
• Solution -gt electro-thermal analysis

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Previous work

• Thermal solvers

Wuns97
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Thermal solvers
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History

• 1977 - Fukahori, coupled set of electro-thermal
  equations to model device
• 1986 - Smith, temperature distribution for GaAs
  FETs, analytical solution
• 1993 - Lee, Allstot, electro-thermal simulation,
  FDM, relaxation
• 1994 - Petegem, relaxation, FEM
• 1996 - Szekely, direct coupling, Fourier series
• 1996 - Szekely, electro-thermal and logi-thermal
• 1997 - Wunsche, relaxation, FEM, transient
  analysis

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TED characteristics

• integration within design framework
• r/w access to design database
• efficient electro-thermal analysis
• sufficiently precise
• fast (thermal, electro-thermal)
• robust in memory usage
• automated
• modular and extensible

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Used approach

• Simulator coupling
• smaller circuit, lower node count, memory
  efficient, faster simulation time
• Analytical solution
• fastest and sufficiently precise
• One extraction, one netlist
• No changes to the device model, no additional
  masks for extraction
• R/W Access to design database

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Electro-thermal loop / Flowchart
Assign new temperatures
N
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Thermal algorithm

• Steady state heat conduction

• Solution for point heat source

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Thermal algorithm

• Kirhoffs integral transformation to accommodate
  kf(T)

• Back
• transform

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Thermal algorithm

• Additional features
• modeled metal interconnects
• substrate depth
• boundary conditions
• element grouping

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Verification against FEM solver Device thermal
model

• GaAs substrate
• temperature dependent conductivity
• 50x0.6mm DFET
• device only
• no metal
• 50 mW dissipation
• boundary conditions
• forced 50oC on the bottom
• side and top walls non conducting

• 3D model constructed for FEM solver (FlexPDTM)
• 5-20k nodes mesh
• 10min execution time, PC, PentiumII

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Mutual heating, 2 DFETs, 30mm spaced

• Superposition of thermal effects
• Dangerous when clustering dissipating devices

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Temperature distribution in presence of metal
interconnects
1 FET with metal

• Thermal conductivity device-metal ? important
  heat flux through metal path
• Over-estimated temperatures if not modeled
• new model required

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New method versus full 3D

• Result- very good match

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Examples
Bi-directional buffer, 0.6mm GaAs
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Bi-directional buffer

• 650 devices
• transient analysis
• 3 iterations (max temperature 144, 65.5, 68 oC)
• thermal analysis - 1 to 10 sec / iteration
• HspiceTM - 2.5min / iteration

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Calculated thermal map

• Different boundary conditions defined for NW and
  SE

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GaAs, operational amplifier

• operational amplifier, GaAs
• different temperatures for parallel devices
• self-heating model not sufficient

Output stage
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Thermally induced offset

• Operational amplifier, GaAs
• local temperature raise (output stage)
• device mismatch
• offset voltage

Constant T
Updated T
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Major contribution

• Development of global methodology allowing
  practical steady-state electro-thermal analysis
  of large integrated circuits
• within much shorter execution time than existing
  one
• applicable for very large circuits
• Development of algorithms necessary to implement
  the methodology
• Development of algorithm allowing thermal
  modeling of integrated circuits with metal
  interconnections
• Electro-thermal evaluation of chosen circuits
  (HBT, GaAs)