Development of Parameterized Templates and RExtraction Tools

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Development of Parameterized Templates and
R-Extraction Tools
Dr. Shamik Sural Assistant Professor School of
Information Technology Indian Institute of
Technology Kharagpur, India
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Agenda

• Team Members
• Previous Work
• New Strategy-based Approach
• Current Status
• Future Work
• Brief Overview of Resistance Extraction

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Project Team at IIT Kharagpur
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Team Members

• Prof. Amit Patra (Principal Consultant)
• Dr. Shamik Sural (Co-consultant)
• GRAs and Interns
• Placement and Routing
• Santosh Biswas
• Subrat Panda
• Baidurya Chatterjee
• Devjyoti Patra (Intern)
• Samrat Mondal (Intern)
• Resistance Extraction
• Abhishek Somani
• Samrat Ray
• Syamantak Das

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Development of Parameterized Templates
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Previous Work
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Object Oriented Template Design

• Hierarchical Approach
• Device Template
• Placement Template
• Routing Template
• Pad Template
• General Requirements
• Design Rule Compliance, i.e., Correct-by-construct
  ion layouts
• Templates to work on a generic set of design
  rules which cover a good number of processes
• Template code to be modular to allow for future
  changes and new recommendations
• Object Oriented approach suits best for writing
  systematically modular code in a hierarchically
  decomposed system

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Salient Features

• Templates are hierarchical composites of objects
• Classes are defined containing private variables
  and methods to access them
• The key object-oriented concepts have been
  incorporated
• Initiative on building an array of essential
  intermediate classes, which are built using the
  SI primitives and can be used to construct
  complex device templates

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Maintainable Code Development

• To improve the readability of codes developed
• Brief overview of the algorithm provided at the
  start of the code
• All functions accompanied with description
• Standard Java nomenclature followed
• Self-explanatory variable names
• Detailed modularization of code

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Example of Class Diagrams used
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Routing Templates Initial Approach

• Classes of Routing problems
• DC routing
• Routing for Matching structures
• Kelvin Routing for Resistance measurement
• Routing of RF structures
• Algorithms used
• Line Probe Routing
• Special techniques
• Connection graph based method for economic
  variable width routing

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Example of a Quad using DC Routing
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New Strategy-based Approach
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New Approach

• A new strategy based approach has been formulated
  
• Depends on the nature of devices and the required
  interconnections
• Devices such as MOSFETs may have various
  connection strategies such as Common Gate, Common
  Substrate Bus or a Substrate Bus only
• Primary goal is to make the placement intelligent
  enough so that the routing involves simpler
  connections between the source and the sink
  terminals
• Strategies being developed for MOSFETs,
  capacitors and via chains

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Placement

• Strategy specific
• Strategy specs drawn up to define the number of
  Pads that a device shall cover
• e.g. 1device/3 Pads for a strategy involving
  MOSFETs
• Devices are categorized in various classes such
  as Small, Medium and Big
• Devices are sorted by their heights and in case
  of equal heights they are sorted by their widths

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Placement

• Placement is carried out on the basis of the
  device categorization
• Devices categorized as Small or Medium are placed
  inside the Quad
• Big devices are placed outside the Quad
• Device placement is carried out in a specific
  sequence such that the problem of overlapping of
  devices of various sizes does not occur

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Placement - Strategies

• Strategy 1 Salient Features
• Low_SD_Modeling_4Terminal_MOSFETS_M1andM2
• M1 and M2 to be used
• 2 dev / 4 pads
• Gate bus
• Substrate bus
• Allow flipped Source-Drain
• S-D resistance constraint

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Strategy 1
PR using Strategy 1
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Placement - Strategies

• Strategy 2 Salient Features
• Low_SD_Modeling_4Terminal_MOSFETS_M1andM2
• To be used primarily for thin gate MOSFETs
• 1 dev / 3 pads
• M1 and M2 for routing
• No Gate bus
• Substrate bus
• Allow flipped Source-Drain
• S-D resistance constraint.

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Strategy 2
Sub
B
D
D-S
D-S
D-S
D
S
G
B
D
D-S
D
S
G
PR using Strategy 2
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Placement - Strategies

• Strategy 3 Salient Features
• 2_terminal_capacitor
• 1 device / 2 pads
• M1 only for routing
• No bus connection involved

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Strategy 3
P R using strategy 3
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Placement of Small Devices
Devices placed inside a quad
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Placement of 100 Devices
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Combination of Placement both Inside and Outside
a Quad
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Routing

• Routing in the new approach is also strategy
  specific
• Nature of the connections of the Terminals to the
  Pads are dependent on the Strategy
• Incorporation of resistance aware routing for
  each strategy

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Routing

• Execution of the Placement Algorithm returns the
  set of Placed Devices and the set of
  interconnections of the various terminals of the
  devices
• We start off by drawing a bus in the MET1 layer
  noting down the bends wherever necessary
  depending on the orientation of the devices
  placed (Strategy 1 specific)
• The second bus is then drawn taking the bend
  points from the metal line drawn in MET1. This
  bus connection is drawn in MET2.

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Routing

• The independent terminals (the ones without the
  bus connections) are then connected to their
  respective pads from the list of connections we
  obtain from the Connection Array
• The resistance aware routing would require a
  different approach where we have to meet Source
  Drain resistance constraints ( SD-Rmax )
• Initial implementation includes a non
  resistance-aware routing

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Current Status
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Resistance Aware Routing

• Currently in the implementation phase of
  Resistance Aware routing for Strategy 1
• The resistance calculation would be done using a
  counting squares method
• The metals can be thickened up to meet the
  resistance constraints
• If a single metal layer say MET1 is unable to
  meet the resistance constraints, then we can use
  2 metal layers in parallel to try to meet the
  constraints
• Places where multiple metal layers are used and
  their widths have to be doubled or tripled up we
  use array of vias

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Resistance Aware Routing

• Via arrays linking two metal layers together are
  to be inserted at a spacing and size determined
  by certain GUI parameters
• The GUI parameters would include via enclosure,
  via space with the latter being a multiple of the
  former
• Routing from the Source and Drain would start off
  in multiple metal layers from inside the bounding
  box and would continue outside using the via
  density indicated above

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Resistance Aware Routing

• The metal width could be doubled up again outside
  the bounding box if such constraints need to be
  met using an array of vias
• Doubling of metal width will be an iterative
  process and incorporated as an algorithmic output
  and not at different levels of debugging or in
  the GUI. The algorithm will thus control this as
  necessary

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Routing of a combination of Small andMedium
Devices
Place and Route of Small and Medium Devices
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A Close Look at Strategy 1

• To be used for P R of MOSFETs
• Source and Drains to have independent connections
  while the Gate and the Substrate are to be
  connected using a bus
• No pad sharing for the Source and the Drain
• Status
• Placement complete for Small, Medium and Big
  Devices
• Non resistance aware routing for Small and
  Medium devices complete while big Devices
  implementation is in progress
• Resistance aware routing implementation also in
  progress

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Place and Route using Strategy 1
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Other Strategies

• Strategy 2
• To be used for MOSFETs
• Placement in the Implementation Phase
• Strategy 3
• To be used for Capacitors
• Placement in the Implementation Phase
• Strategy 4
• To be used for Via Chains
• Specs are being drawn up

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Future Work
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Future Work

• Specification finalization and implementation of
  other strategies for MOSFETs and 2 terminal
  devices
• Make all the routing strategies resistance aware
• Other types of routing

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Development of Resistance Extraction Tools
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RdsON Resistance Extraction Tool
FLOWCHART OF THE ALGORITHM
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Identification of Basic Cells
IDENTIFIED AS BASIC CELL -2
IDENTIFIED AS BASIC CELL-1
Power Array
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Power Array Example Identify Different Basic
Cells
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Breaking the Array into different Basic Cells
Basic cell - 2
Power Array
Basic cell-1
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Identify Basic Cell - 1
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Identify Basic Cell - 2
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Thank You