Programmable Logic Technologies

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ECE U322Digital Logic Design
Nov 30 2005

• Lecture 32
• Programmable Logic Devices
• ROMs, PLAs and PALs
• FPGAs
• Reading Marcovitz 5.7, 8.3
• Homework 8 Due Monday Dec 5th

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Programmable Logic Devices

• Read-Only Memory (ROM)
• Programmable Logic Array (PLA) device
• Programmable Array Logic (PAL) device
• Complex Programmable Logic Device (CPLD)
• Field-Programmable Gate Array (FPGA)

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Programmable Logic

• Regular array of logic
• Specialized to a specific logic function after
  the regular array has been designed
• Programming the device
• Hardware procedure that specifies the bits that
  are inserted into the hardware configuration of
  the device.
• Programming the device specializes the array.

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Programmable Logic

• Want to implement combinational logic with a
  regular array
• Why?
• Predictable area
• Easy to make changes
• Start with SOP form
• Minimize or not?
• Depends on type of programmable logic

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Programmable Logic

• Logic can be
• Mask Programmable
• Programmed when chip is fabricated
• In the factory
• Field Programmable
• Programmed in the field
• Can be changed after chip has been fabricated

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Programmable Logic

• Field Programmable Logic can be
• Program once
• Can program it in the field, but then cannot make
  changes -- fuse, antifuse
• Reprogrammable
• Electrically Erasable, UV Erasable, Flash Memory
  based,
• Reconfigurable Reprogrammable while circuit is
  runnning SRAM based
• This is what you are using in lab

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Programmable Logic Technologies

• Control connections
• Mask programming
• Place transistors when fabricating chip
• Antifuse
• Burn once in the field
• SRAM bits driving the gate of an n-MOS transistor
  or stored in a look up table
• Reconfigurable in the circuit
• This is what you are using in lab !

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Combinational Logic with Programmable Hardware

• Implement logic in SOP form
• Multiple inputs, multiple outputs
• ROM Read Only Memory
• Implement logic without simplifying
• PLAs and PALs
• Simplify logic before implementing it

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Read-Only Memory (ROM)
ROM stores the truth table for my function May
have many different sizes of ROM 10 inputs, 12
outputs _____ locations
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Internal logic of a 32 x 8 ROM
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Conventional Symbol for OR gate
Array Logic Symbol for OR gate
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Programming the ROM
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Programming Technologies for ROM

• Mask programming
• ROM is called simply a ROM.
• Fuses
• Referred to as a programmable ROM (PROM)
• Erasable floating-gate technology
• Referred to as an erasable, programmable ROM
  (EPROM)
• Electrically erasable technology
• Electrically erasable, programmable ROM (EEPROM
  or E2PROM).

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• Example Implement a BCD-to-Seven-Segment
  Decoder Using a ROM

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BCD to seven segment decoder on a 32 x 8 ROM
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Basic Configuration of Three Types of PLDs
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PLA Unprogrammed Device
All possible connections are available before
programming
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PLA Logic Implementation
Key to Success Shared Product Terms
Equations
Example
Personality Matrix
Input Side
1 asserted in term 0 negated in term - does
not participate
Output Side
1 term connected to output 0 no connection to
output
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PLA Logic Implementation
Example Continued - Programmed part
Unwanted connections are "blown"
Note some array structures work by making
connections rather than breaking them
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PLA Logic Implementation
Unprogrammed device
Alternative representation for high fan-in
structures
Short-hand notation so we don't have to draw all
the wires! X at junction indicates a connection
Programmed device
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PLA Logic Implementation
Multiple functions of A, B, C
F1 A B C F2 A B C F3 A B C F4 A
B C F5 A ? B ? C F6 A ? B ? C
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PALs and PLAs
PAL AND array is programmable, OR array is
fixed at fabrication PLA  Both AND and OR arrays
are programmable
A given column of the OR array has access to only
a subset of the possible product terms
PAL devices are smaller Programmable
connections take up space
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PALs and PLAs

• PLA is the most flexible
• One PLA can implement a huge range of logic
  functions
• BUT many pins, large package, higher cost
• Each programmable connection needs extra space
• PALs are more restricted you trade number of OR
  terms vs. number of outputs
• Many device variations needed
• Each device is cheaper than a PLA

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PAL Logic Implementation
K-maps
Design Example BCD to Gray Code Converter
Truth Table
Minimized Functions
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Discrete Logic Implementation
Code Converter Discrete Gate Implementation
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PAL Logic Implementation
Minimized Functions
4 product terms per each OR gate
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Example Magnitude Comparator

• Inputs ABCD Outputs EQ, NE, LT, GT

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PLA Logic Implementation
Another Example Magnitude Comparator
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Complex Programmable Logic Devices

• Complex PLDs typically combine PAL combinational
  logic with FFs
• Organized into logic blocks
• Fixed OR array size
• Combinational or registered output
• Some pins are inputs only
• Usually enough logic for simple counters, state
  machines, decoders, etc.

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16V8 CPLD
OLMC (Output Logic MacroCell) has OR, FF, output
multiplexer and I/O control logic. Note that
OLMC output is fed back to input matrix for use
in other OLMCs.
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Field Programmalble Gate Arrays (FPGAs)

• FPGAs have much more logic than CPLDs
• 2K to 400K equivalent gates
• Requires different architecture
• FPGAs can be RAM-based or Flash-based
• RAM FPGAs must be programmed at power-on
• External memory needed for programming data
• May be dynamically reconfigured
• Flash FPGAs store program data in non-volatile
  memory
• Reprogramming is more difficult
• Holds configuration when power is off

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FPGA Structure

• Typical organization is 2-D array
• Configurable logic blocks (CLBs) contain
  functional logic
• Combinational functions plus FFs
• Complexity varies by device
• CLB interconnect is either local or long line
• CLBs have connections to local neighbors
• Horizontal and vertical channels use for long
  distance
• Channel intersections have switch matrix
• IOBs (I/O logic Blocks) connect to pins
• Usually have some additional C.L./FF in block

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FPGA Structure
IOB
IOB
IOB
IOB
Input/Output Block
CLB
CLB
CLB
CLB
Switch Matrix
SM
SM
SM
CLB
CLB
CLB
CLB
SM
SM
SM
CLB
CLB
CLB
CLB
Configurable Logic Block
SM
SM
SM
CLB
CLB
CLB
CLB