COMP 206: Computer Architecture and Implementation

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COMP 206Computer Architecture and Implementation

• Montek Singh
• Mon., Nov. 18, 2002
• Topic Main Memory (DRAM) Organization contd.

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Achieving Higher Memory Bandwidth
Fig. 5.27HP3
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Improving Memory Chip Performance

• Several techniques to get more bits/sec from a
  DRAM chip
• Allow repeated accesses to the row buffer without
  another row access time
• burst mode, fast page mode, EDO mode,
• Simplify the DRAM-CPU interface
• add a clock to reduce overhead of synchronizing
  with the controller
• synchronous DRAM (SDRAM)
• Transfer data on both rising and falling clock
  edges
• double data rate (DDR)
• Each of the above adds a small amount of logic to
  exploit the high internal DRAM bandwidth

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Conventional DRAM Architectures
16 Mb (16M?1) chip One 4096?4096 array of data
bits
16 Mb (1M?16) chip 16 1024?1024 arrays of data
bits

• Interface is either the original asynchronous
  interface or one of the many recent minor
  modifications of it
• RAS Row Address Strobe
• CAS Column Address Strobe
• DRAM asynchronously controlled by processor

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Basic Mode of Operation

• Slowest mode
• Uses only single row and column address
• Row access is slow (60-70ns) compared to column
  access (5-10ns)
• Leads to three techniques for DRAM speed
  improvement
• Getting more bits out of DRAM on one access given
  timing constraints
• Pipelining the various operations to minimize
  total time
• Segmenting the data in such a way that some
  operations are eliminated for a given set of
  accesses

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Nibble (or Burst) Mode
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----
CAS CAS CAS CAS RA CA D1 D2 D3 D4

• Several consecutive columns are accessed
• Only first column address is explicitly specified
• Rest are internally generated using a counter

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Fast Page Mode
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----
CAS CAS CAS CAS RA CA1 CA2 CA3 CA4 D1
D2 D3 D4

• Accesses arbitrary columns within same row
• Static column mode is similar

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EDO Mode
RAS ---- ---- ---- ---- ---- ---- ---- ---- ----
CAS CAS CAS CAS CAS CAS CAS RA CA1 CA2 CA3 CA4 C
A5 CA6 CA7 D1 D2 D3 D4 D5 D6

• Arbitrary column addresses
• Pipelined
• EDO Extended Data Out
• Has other modes like burst EDO, which allows
  reading of a fixed number of bytes starting with
  each specified column address

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Evolutionary DRAM Architectures

• SDRAM (Synchronous DRAM)
• Interface retains a good part of conventional
  DRAM interface
• addresses multiplexed in two halves
• separate data pins
• two control signals
• All address, data, and control signals are
  synchronized with an external clock (100-150 MHz)
• Allows decoupling of processor and memory
• Allows pipelining a series of reads and writes
• Peak speed per memory module 800-1200 MB/sec

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Revolutionary DRAM Architectures

• Examples
• RDRAM (Rambus DRAM)
• MDRAM (MoSys DRAM)
• Salient features
• Many smaller memory banks interleaved on one chip
• Protocol based architecture
• Narrow, fully multiplexed communication protocol
• Example RAMBUS (RDRAM, DRDRAM)
• Each chip is more like a memory system than a
  component
• Interleaved memory and a high-speed interface
• Packet-switched bus (split transaction bus)
• Chip can return variable bytes from a single
  request, performs own reset, transfers on both
  clock edges
• Narrow bus (1-2 data bytes)
• Upto 3 transactions can be done concurrently
• Internally, 72-bit wide bus with 5 ns cycle time
• Up to 1600 Mbps peak bandwidth
• Expensive!

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Other types of Memory

• ROM Read-only Memory
• Flash ROM which can be written once in a while
• Used in embedded systems, small microcontrollers
• Offer IP protection, security

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Memory Interleaving

• Goal Try to take advantage of bandwidth of
  multiple DRAMs in memory system
• Memory address A is converted into (b,w) pair,
  where
• b bank index
• w word index within bank
• Logically a wide memory
• Accesses to B banks staged over time to share
  internal resources such as memory bus
• Interleaving can be on
• Low-order bits of address (cyclic)
• b A mod B, w A div B
• High-order bits of address (block)
• Combination of the two (block-cyclic)

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Low-order Bit Interleaving
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Mixed Interleaving

• Memory address register is 6 bits wide
• Most significant 2 bits give bank address
• Next 3 bits give word address within bank
• LSB gives (parity of) module within bank
• 6 0001102 (00, 011, 0) (0, 3, 0)
• 41 1010012 (10, 100, 1) (2, 4, 1)