HighSpeed Memory Architectures

1
High-Speed Memory Architectures

• Andreas Burg Martin Hägele

2
Motivation

• Memory-bandwidthbottleneck
• Modern multimedia applications require higher
  datarates

3
Architecture-Overview

• DRAM Dynamic RAM
• FPM Fast Page ModeEDO Extended Data Output
• SDRAM Synchronous DRAM
• RDRAM Rambus DRAM
• CDRAM Cache DRAMEDRAM Enhanced DRAM
• VRAM Video RAM
• RamLink SyncLink

4
DRAM CORE
Memory Array
Decoder
RAS
PreAmps
Address
CAS
DATA
5
FPM/EDO

• Based on standard DRAM core
• Fast random access on data within a row (single
  RAS, multiple CAS)
• EDO extended data valid time
• RecommendationDo NOT use in new designs!

6
SDRAM

• Fully synchronous interface
• Pipelined operation
• Command oriented
• Configurable burst mode delays
• Multiple banks for hidden precharge
• more flexibility for highspeed access sequences

7
RDRAM

• Interface (Rambus Channel)
• 9-Bit communication port
• 1-Bit control port
• packet oriented
• request / Acknowledge
• Transfer rates up to 500MBytes/s
• PLL for clock synchronisation

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CDRAM EDRAM

• Integrated SRAM cache
• Access speed up to 100MHz
• Synchronous operation
• Drawback
• copy-back cycles slow down the system(some
  CDRAMs allow hidden copy-back operations)
• cache operation not controllable

9
Video RAM

• Specialized for video applications
• Dual ported
• unidirectional serial port for video CODEC
• random access port
• Synchronous operation
• High price

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RamLink SyncLink

• Communication interface
• Ring topology
• Controlled by packet scheduler
• 500MBytes/s without major layout requirements
• Synchronous double-edge triggered operation
• Targeted for multiprocessor systems

11
Conclusions

• Almost no improvement in true random access time
• FPM/EDO almost vanished from the market
• SDRAM is the most commonly used standard
• very fast
• easy application
• low cost (very high volume in PC industry)
• Many other specialized architectures(e.g. for
  video applications DDR SGDRAM)