STR910F Series Technical Overview

1
STR910F Series Technical Overview

• 32-bit ARM9-based Flash
  Microcontrollers

2
Whats In This Presentation?

• A technical overview of each major feature and
  function of STR91xF MCUs
• Please see the STR7/STR9 MCU Product Presentation
  for general product and tool information

3
Click Any Block to See More Info
256KB 32KB, 512KB 32KB Burst Flash
JTAG
ETM
2 x I2C
Other Features
ACCEL
2 x SPI
DSP Functions
64KB or 96KB SRAM
3 x UART / IrDA
Memory Map
Up to 80 I/Os
Low Power Modes
8 Channel DMA
4 x 16-bit Timer
1 x Ethernet MAC w/DMA
Battery Standby
Intr Control 33 Priority Lvls
Watchdog
WUU
1 x USB FS Device w/DMA
RTC
EMI, Data x8 or x16
Clock Control
External Components
8 x 10-bit ADC
1 x CAN 2.0B
PLL
Detailed Block Diagram
POR LVD BOD
Voltage Inputs 3.0V I/O, 1.8V Core, Opt. Battery
for RTC and SRAM
Crystal Inputs Main Optional RTC
Configuration Tool
3-Phase Motor Control
4
Thank You
5
STR912F
TO I/O MATRIX
TO I/O MATRIX
ETM9
MII
PHY
DUAL VIC
JTAG
10/100 ETHERNET MAC
64 KB or 96 KB SRAM
32 KB FLASH
32 B OTP
USB FULL SPEED DEVICE
256 KB or 512 KB MAIN FLASH
ARM966E-S RISC CPU 96 MHz
D-TCM
I-TCM
BURST FLASH CONTROLLER
ARBITER
DMA
AMBA
6-96 MHz OUT, PLL
4-25 MHz SYSCLK
CRYSTAL
AHB
ADC REFERENCE
VREF
AHB / APB BRIDGE 1
AHB / APB BRIDGE 0
8 CHANNEL DMA CONTROLLER
2.7V to 3.6V I/O SOURCE
VDDQ
1.8V CORE SOURCE
CLK PWR CNTL
VDD
AUTOMATIC SWITCH
REQUESTS FROM USB, SPI, UART, I2C, TIMERS
BATTERY BACKUP
VBATT
WATCHDOG
32 KHz CLK
SUPER-VISOR
CRYSTAL
TO SRAM
APB1
APB0
RTC with TAMPER
SEPARATE POWER DOMAIN
WAKE UP UNIT
EXT MEMORY
2 X SSP (SPI)
CAN 2.0B
3 X UART w/IrDA
8 x ADC 10-bit
3ph INDUCTION MOTOR CONTROL
4 x TIMERS 16-bit
2 X I2C
FROM ETM9
FROM MII
80 GPIO
I/O SWITCH MATRIX
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
8
8
8
8
8
8
8
8
8
8
ANALOG
CPU SYSTEM
I/O
MEMORY
TIMER
6
ARM9E Core Architecture Advantages

• Harvard Architecture with 5-Stage Pipeline
• Tightly Coupled Memories (TCM)
• Buffered Write Backs to Data Memory
• Single-Cycle DSP Instructions
• The ARM966E-S core was chosen because it
• Does not include a costly cache memory (die size)
• Has Multi-Master AHB

What is the difference between ARM9E and ARM7TDMI?
7
ARM966E Benefits vs. ARM7TDMI

• 5 stage pipeline reduces Clocks Per Instruction
  (CPI)

• Harvard Architecture improves Load/Store
  performance

• Tightly Coupled Memories (TCM), more
  deterministic
• AHB and DTCM Write Buffers for less stalls

• ARMv5TE Architecture with DSP Instructions
  (1-cycle 32x16 MAC, Saturated Math, and
  others)

F Fetch D Decode E Execute M Memory
Read W Memory Write-Back
8
STR910 Enhancements of ARM966E

• Pre-Fetch Queue (PFQ) and Branch Cache (BC)
• PFQ always looks ahead fetching instructions
  during idle bus cycles
• BC remembers last four jumps, immediately loading
  PFQ upon jump (branch)

• 32-bit wide Single-Cycle SRAM
• 32-bit wide Burst Flash Memory
• Burst Memory interface Operates up to 96MHz (10.4
  ns) when retrieving Sequential 1-Word
  Instructions

9
Pre-Fetch Queue and Branch Cache
What happens when instructions are not
sequential? Will PFQ stall?

• BC holds 4 instructions for each of 4 most recent
  branches
• BC loads PFQ with all 4 instructions into PFQ if
  branch address matches

• PFQ stall reduced upon a branch match
• 5th BC entry has instructions to read VIC
• PFQ will not flush when CPU reads a literal (a
  constant in instruction memory)

10
STR910F DSP Capability

• STR910F architecture compliments the ARM9E core
• Single cycle DSP Instructions (MAC, Saturated
  Math, CLZ)
• Large Flash for Complex Algorithms and Look Up
  Tables
• Large SRAM for Data Capture and run time storage
  of Coefficients
• Harvard Architecture great for DSP functions
• Benefits of Harvard Architecture and single-cycle
  DSP instructions clearly demonstrated by FFT
  performance with Code in Flash and Coefficients
  in SRAM
• More FFT measurements (code in Flash,
  coefficients in SRAM)
• 64-pt FFT in 32 usec, 128-pt FFT in 160 usec

11
DSP Benchmark Results
6 times slower
Normalized Time Required to Complete 1024 point
FFT
3.15 times slower
Competitor 2
1.0 (Normalized, 787 usec)
Competitor 1
STR91XF, 96MHz. Code in Flash,
Coefficients in SRAM (Harvard Architecture)
ARM7, 60MHz. Code in Flash, Coefficients in Flash
or SRAM
ARM7, 48MHz. Code in Flash, Coefficients in Flash
or SRAM
12
Why is DMA Important?

• Direct Memory Access (DMA) offloads the CPU
• STR910F has 17 peripherals
• What if they all need to transfer data at same
  time?
• CPU would be over-loaded
• Real-time performance would end
• Independent control
• CPU sets up DMA channels for peripheral only once
• DMA channels automatically manage source and
  destination of data
• DMA channels competes with the CPU for access to
  the SRAM

13
ARM7 Without DMA
Peripheral Data Transfers Directly Impact
Performance
Instruction fetch
Memory Controller
FLASH (Code)
INSTRUCTIONS DATA
PERIPHERALS
ARM7TDMI CORE
SRAM (Data)
AHB
Load register

• All data transfers under software control
• ARM is load/store architecture requiring data to
  be read from peripheral into internal register
  before being written from internal register to
  SRAM
• ARM7 core has to wait for peripheral read to
  complete stalling ARM7 core for slow
  peripherals
• ARM7 Core not available for other operations
  while transferring data
• Instructions and Data share same bus
• CPU stalls during Data read/write

14
ARM7 With DMA
Removes Software Overhead
Memory Controller
FLASH
INSTRUCTIONS DATA
PERIPHERALS
ARM7TDMI CORE
SRAM
DMA
AHB
DMA

• DMA transfer frees CPU for other tasks
• Memory Controller becomes the bottleneck
• Instruction Fetch, Data Read/Write and DMA all
  trying share same pipeline through the Memory
  Controller
• DMA transfer will stall CPU
• CPU Instruction fetch or Data Read/Write will
  stall DMA
• CPU cannot fetch instructions and read/write data
  in same cycle

15
STR910
Efficient DMA and Rapid Data Flow
USB UART SPI I2C TIMERS
INSTRUCTIONS
PFQ/BC
BURST FLASH
ITCM
ENET
ARBITER
DATA
DTCM
1 DMA
8 DMA
SRAM
ARM966 CORE
DMA
AHB

• Simultaneous ARM9 Core Execution and DMA Transfer
• ARM9 Core Executing From Flash through ITCM
• Data transfers to/from SRAM

• Arbiter shares SRAM access between ARM9 Core and
  DMA/AHB
• Special design guarantees access to each
  requestor on every other cycle

16
DMA Data Specifics

• The AHB bus is freed up from normal
  Data/Instruction access via the ARM 966 TCMs
• Provides increased AHB bandwidth for DMA units
• STR910 has Two DMA Units on the AHB bus
• A dedicated DMA unit for Ethernet MAC
• Second General Purpose DMA unit
• 8 programmable channels
• Peripherals served (USB, SPI, I2C, UART, Timers,
  EMI and external request pins)
• Single word and burst transfers
• Memory-to-peripherals and memory-to-memory
  transfers

17
STR910 Dual DMA Controllers

• Each DMA Controller is AHB Bus Master taking full
  advantage of ARM966 Harvard Architecture for
  simultaneous CPU execution and DMA transfer
• ARM966 core executing code from flash through
  i-TCM
• DMA AHB Bus master transferring data into or out
  of SRAM
• Dedicated Ethernet DMA Controller
• Second General Purpose DMA unit
• 8 programmable channels
• Peripherals served (USB, SPI, I2C, UART, Timers,
  EMI and external request pins)
• Single word and burst transfers
• Memory-to-peripherals, memory-to-memory and
  peripheral-to-peripheral transfers
• Scatter or gather DMA using linked lists

18
GP DMAC Scatter Gather DMA
Memory
No CPU Intervention Required!

• A series of Linked Lists define source and
  destination
• Each linked list defines
• Source Address
• Destination Address
• Transfer Width
• Source/Destination burst size
• Next Linked List Address

• First linked list (source address 0x0A200,
  destination peripheral, transfer width, transfer
  size 3072 bytes 0x0C00, burst size, next linked
  list address)

• Next linked list (source address 0x0B200,
  destination peripheral, transfer width, transfer
  size 3072 bytes 0x0C00, burst size, next linked
  list address)

• And so on..

19
DMA Acceleration for USB Transfer
CPU OVER LOAD !!!!
20
DMA Speeds Ethernet Transfers
Equivalent Raw Ethernet data frames transferred
between Ethernet MAC and SRAM

• DMA Controller manages data transfer with little
  CPU intervention
• Programmable TX and RX FIFO threshold
  automatically triggers AHB transfers
• DMA supports fixed address, auto-incrementing and
  circular buffers in CPU memory
• Support for chained descriptors once DMA
  transfer completes it can either interrupt CPU or
  fetch new DMA descriptor

21
Very Large SRAM

• 96KB is largest in class today (Flash ARM MCUs)
• Why is large SRAM important?
• Combination of RTOS, TCP/IP stack, USB stack, DSP
  functions, complex application consume SRAM very
  quickly
• Large SRAM needed to cover this, plus
  communication packet buffers
• Larger packets transferred on serial comm lines
  mean less overhead
• Less overhead means higher transmission
  throughput
• CPU core can execute code from SRAM if desired
• SRAM contents can be automatically backed up by a
  voltage on VBATT pin if desired (only 0.5 uA at
  25oC)

22
Very Large Flash Memories

• Up to 588 KB of dual-bank burst Flash memory
• 100K erase cycles, 20 year data retention
• Large size supports needs
• RTOS application
• TCP/IP code, embedded HTML page(s)
• Multinational products, multi-application
  products
• Self-diagnostic code or Data recording
• Dual bank architecture
• True read-while-write capability, good for safe
  In-Application-Programming and EEPROM emulation
• Write by single-word, erase by sector
• 8usec/word write time, 8 sec erase for 512KB bank
  , 4 sec erase for 256KB bank, 700 usec erase for
  32KB bank
• Smaller secondary Flash has four 8KB sectors
• Larger primary Flash has either four or eight
  64KB sectors
• Can boot from either Flash memory, programmable
  option

23
STR910 Memory Map

• Single Linear Address Range
• 4 Gigabyte range
• Harvard busses transparent to firmware
• Code and data separated in silicon
• High Speed Peripherals on AHB
• Lower Speed Peripherals on APB
• Firmware accesses APB through a bridge, or
  window, on the AHB
• Separate Ranges for Write Buffer
• Peripherals have two address ranges
• One for buffered writes and another for
  non-buffered writes
• Buffered writes increase overall performance
• Non-buffered writes guarantee data coherency
• Dual Flash Bank Memories
• MCU can write/erase one while reading other
• Either Flash can reside at boot location (address
  0x00000000)
• Bank order is user defined

24
OTP Specifics

• 32 bytes of OTP memory
• Ideal for storing MAC address, serial numbers,
  factory calibration constants, or other permanent
  data
• Programmed once though JTAG interface or by CPU
• OTP bytes can be read by either JTAG or the CPU
• Once programmed these bytes can never be altered
• 2 Reserved Bytes for CPU rev ID and MAC Address

25
Low-Power Modes
26
Low-Power Modes

• Full performance, individual Periph Clocks can be
  gated on/off
• Clock speed scaled as needed to balance perf. and
  consumption
• Min Interrupt Response Time 280 nsec (96 MHz,
  FIQ interrupting NOP stream)

RUN

• Specify which Periph Clocks will stop before
  entering Idle
• Exit Idle from Ext reset, WDG reset, Intr, RTC
  alarm, Wake-up Unit
• Interrupt Response Time XX nsec

IDLE

• CPU running at 32KHz, switch to 96MHz upon
  Interrupt
• Can do very simple tasks between receiving an
  Interrupt. Low average pwr
• Max Interrupt Response Time 3.6 msec

WFI

• All clocks off except for RTC and Wake up Unit
• Exit Sleep from Ext reset, RTC Alarm, Wake-up
  Event
• Max Interrupt Response Time 3.6 msec

SLEEP

• Entire device quiescent except for RTC and 32KHz
  osc pads
• Restart from voltage returning to VDD pins
• Min Interrupt Response Time 13.6 msec (includes
  POR)
• Optionally backup SRAM contents for an additional
  5 uA

BATT
27
Battery Standby Circuit RTC/SRAM

• Battery standby circuit isolated from other
  supplies
• Can choose to backup both RTC and SRAM, or just
  RTC
• Automatic crossover switch to VBATT pin when main
  drops
• RTC backup draws only
• 0.3uA max at room temp of 25C
• 0.9uA at max temp of 85C
• 0.0uA while main CPU supply (VDD) is present.
• If using SRAM back-up option
• Additional draw on VBATT pin is 5uA at 25C, 85uA
  at 85C

28
Supervisor Specifics

• STR910 System Supervisor monitors system and
  environmental inputs
• Generates an Interrupt, System Reset or Global
  Reset depending on nature of input
• Global (Cold) Reset clears all functions of
  STR910
• System (Warm) Reset clears all but Clock Control
  Unit (CCU) settings

29
Typical Surrounding Components

• Dual voltage regulator 3.3 V and 1.8 V
• System Clock Xtal (4 25 MHz)
• RTC Xtal (32KHz)
• Ethernet PHY (STE100P) and cable
  connection
• Decoupling caps between all power and
  ground
• JTAG, resistors

1 TO2633 capacitors

1 low cost Xtal2 capacitors


1 low cost Xtal2 capacitors


1 64LQFP pkg (transformer in RJ45)
LQFP128

13 capacitors
7 pull up / pull down resistors

31 components
30
ADC Specifics

• 8 Ch/10-bit successive approximation
• Fast conversion time, as low as 0.7uS
• Single, scan or continuous modes
• Independent Supply and Ref Voltage
• External AVREF for better accuracy on low voltage
  inputs
• LQFP128 and BGA144 pkgs only
• Analog watchdog mode with two thresholds
• Low power standby mode
• Total Unadjusted Error (TUE)
• /- 2 LSB (4 counts) typical

31
3-Phase MC Specifics

• Six PWM Outputs
• Three outputs generated by 10-bit PWM counter
  (phase U, V, W)
• Complementary outputs generated for each phase
• Classic or zero-centered PWM generation modes
• 6-bit dead-time generator for each output
• 8-bit repetition counter
• Rotor speed measurement (16-bit resolution)
• Schmidt trigger tachometer input
• Hardware asynchronous emergency stop
• Dedicated CPU interrupt with 8 flags

32
Interrupt Control and Wake-Up

• 5 intr from wake up unit
• One is logical or of 32 inputs to wake up unit
• Remaining 4 are groupings of 8 inputs
• Interrupt sources for wake up unit are 30
  external inputs (from enabled GPIO), RTC
  Interrupt and USB resume interrupt.
• 27 intr from on-chip periphs
• Any of the 32 intr sources can be assigned to
  Fast Interrupt reQuest (FIQ)
• IRQ is vectored interrupt and is logical OR of
  all 32 Interrupts
• Priority levels can be assigned by MCU firmware
• Wake-up Unit reamins powered on during sleep mode.

33
Fast Interrupt reQuest (FIQ)

• Non-vectored interrupt
• CPU executes without need to determine priority
  or source
• FIQ is last vector in vector table allowing
  interrupt handler to run sequentially from FIQ
  vector
• FIQ has own dedicated banked registers allowing
  faster context switch
• Any one of the 32 interrupt sources can be
  assigned to FIQ

34
Interrupt Request (IRQ)

• Vectored Interrupt
• Logical OR of 32 Interrupt Sources
• VIC Hardware resolves priority level
• ISR reads VIC
• To determine interrupt source
• To read vector address for jump to service code
• STR910 Branch Cache Minimizes Interrupt Latency
• Eliminates first memory access required by
  traditional ARM Architectures

35
IRQ Response
ARM MCU with VIC
STR910 with VIC BC
ARM MCU without VIC
CPU Jumps to 0x18 CPU jumps to common handler CPU
analyses status CPU jumps to interrupt handler
CPU Jumps to 0x18 CPU jumps to interrupt handler
CPU Jumps to 0x18 CPU jumps to interrupt handler
Always in Branch cache!
0x18
0x18
0x18
3 non sequential memory accesses Common handler
required to determine interrupt source
2 non-sequential memory accesses but 0x18 is
always in cache No need for common handler
2 non-sequential memory accesses No need for
common handler
SLOW
FASTER
36
FIQ Response
STR910
CPU Jumps to 0x1C
1 non-sequential memory accesses FIQ ISR located
at 0x1C
0x1C
FASTEST
37
Clock Control Unit (CCU)

• CCU generates Master System Clock (fMSTR) from
  one of three sources selected by firmware
• Main External Crystal or Oscillator fOSC
  (default)
• RTC External Crystal or Oscillator fRTC
• PLL Output fPLL
• CCU generates system clocks from fMSTR
• CPU clock fCPUCLK
• AHB high-speed peripheral bus clock fHCLK
• AHB peripheral bus clock fPCLK
• EMI external bus clock fBCLK
• FMI flash memory clock fFMICLK
• UART Baud Generators fBAUD
• Standard Timerss fTIM01 and fTIM23
• USB fUSB
• USB Interface Clock fUSB comes from one of three
  sources
• fMSTR at 48MHz
• fMSTR at 96MHz with divide-by-two
• External 48 MHz on pin P2.7
• Ethernet MAC Clock comes from one of two sources
• 25 MHz from Main Oscillator (fOSC) output from
  P5.2

38
Clock Control Unit
39
CCU Operational Example
40
PLL Specifics

• Input frequency range
• 4MHz to 25MHz
• Fractional output frequencies can be produced
• Example 25MHz in can produce 96MHz out
• Fast Lock Time, 300 usec Typical
• Low Jitter
• 2 ns maximum

41
RTC Specifics

• Self-isolation Operation
• RTC continues operation during power down or main
  digital supplies drop out
• Automatically switches to alternate voltage
  source (e.g.battery) connected to VBATT pin
• Isolated 32KHz osc circuit continues to operate
  from external crystal
• Max current draw on VBATT pin for RTC is less
  than 0.9 uA across all temp range
• Tamper Detect if tamper event occurs
• RTC time recorded in locations which are
  backed-up by VBATT voltage
• SRAM standby voltage source optionally cut off to
  invalidate SRAM contents

42
JTAG Interface Basic Connections
43
JTAG Specifics

• JTAG Interface
• 5 standard signals (JTDI, JTDO, JTMS, JTCK, JTAG)
  complying with IEEE-1149.1 specification
• Additional JRTCK (return TCK)
• Not required if ARM core clock is 10 times JTCK
• Required to pace JTCK if ARM core clock less than
  10 times JTCK
• In-System Programming
• Program and erase Main and Second Flash through
  JTAG
• Program OTP
• Configure STR91xF selections, such as LVD
  threshold, Flash boot bank, etc.

• Boundary Scan
• All pins except JTAG, Oscillator Inputs and
  TAMPER_IN
• JTAG Debug using ARM EmbeddedICE-RT logic
• Halt or Monitor mode
• 2 breakpoints/watchpoints, run, halt, single step
• JTAG Security Bit
• When set disables all JTAG operations except
  Full Chip Erase
• Device fully usable again after Full Chip
  Erase, but any OTP bytes that were programmed
  will remain unchanged.

44
Embedded Trace Module (ETM) Specifics

• Embedded ETM9 adds additional debug capability
• Real-time instruction flow Trace
• Trace filtering and triggering
• Dedicated 9-pin ETM interface in conjunction with
  JTAG interface
• ETM interface can be re-used as GPIO once
  development is finished
• External Trace Port Analyzer connects to STR91xF
  through ETM connector and to host PC though
  USB2.0 or Ethernet
• ETM connector includes ETM and JTAG signals

45
11 Communication Interfaces

• Ethernet MAC with DMA
• USB 2.0 Full Speed Device
• CAN 2.0B Interface
• 3 Independent UARTs
• 2 Independent I2C
• 2 Independent SSP (SPI, SSI and Microwire)
• 8/16 External Memory Interface (EMI) Bus

46
Ethernet Specifics

• IEEE-802.3-2002 compliant Media Access Controller
• Data encapsulation
• Frame assembly before transmission
• Frame parsing and error correct during
  transmission
• MAC access control
• Initiation of frame transmission and recover from
  transmission failure
• Dedicated 32-bit burst DMA channel
• Direct SRAM to MAC transfers of transmit frames
• Direct MAC to SRAM transfers of receive frames
• Descriptor chain management

MII
MII Media Independent Interface
47
DMA Speeds Ethernet Transfers
Equivalent Raw Ethernet data frames transferred
between Ethernet MAC and SRAM

• DMA Controller manages data transfer with little
  CPU intervention
• Programmable TX and RX FIFO threshold
  automatically triggers AHB transfers
• DMA supports fixed address, auto-incrementing and
  circular buffers in CPU memory
• Support for chained descriptors once DMA
  transfer completes it can either interrupt CPU or
  fetch new DMA descriptor

48
Excellent TCP/IP Throughput
CPU running at full speed, 96MHz, and using
TCP/IP stack from Micrium

• TCP/IP protocol requires significant processing
  power
• When providing 8.5 Mbits/sec (OK for streaming
  video), the STR910 have 50 of its CPU bandwith
  available for other tasks
• How does this compare with another embedded
  processor?
• An ARM920T CPU running at 180MHz using the same
  TCP/IP stack managed 24 Mbits/sec TCP/IP
  throughput using 100 of CPU bandwidth
• STR910F running at 96MHz managed 16.1 Mbits/sec
  using 100 CPU bandwidth. By comparison of ratio,
  this is better than the ARM920T case.

49
USB Specifics

• USB Device Interface
• Low speed and full speed (12 Mbps) operation, USB
  2.0 compliant
• Isochronous, bulk, control and interrupt
  endpoints
• Configurable up to 10 double-buffered endpoints
• USB suspend resume operation
• Built-In PHY for direct connect
• Packet Buffer Interface (PBI)
• Dual port 2Kbyte SRAM
• PBI manages buffers in SRAM
• Special double buffer support for Isochronous and
  Bulk transfers
• DMA
• Direct PB SRAM to System SRAM of receive packets
• Direct System SRAM to PB SRAM of transmit packets
• Linked list descriptor chain support

50
DMA Acceleration for USB Transfer
CPU OVER LOAD !!!!
51
CAN 2.0B Interface

• Standard Bosch CAN interface
• Message handler takes care of low level CAN bus
  activity
• Acceptance filtering
• Transfer of messages between CAN bus and Message
  SRAM
• Handling of transmission requests
• Interrupt handling
• CPU has access to Message SRAM and Message
  Handler through 38 control registers

52
Three UARTS w/DMA

• UART0 supports full modem control signals
• UART0, UART1, UART2
• Similar to industry standard 16C550 UART
• Maximum Baud Rate 1.5M bits per second
• Separate 16-bit deep FIFOs for transmit and
  receive
• Programmable FIFO trigger levels
• Programmable Baud Rate Generators based on CCU
  Master Clock or Master Clock divided by 2
• Programmable serial data lengths 5, 6, 7, or 8
  bits with start bit and 1 or 2 stop bits
• Programmable selection of even, odd or no-parity
  bit bit generation and detection
• False start bit detection
• Line break detection and generation
• Support of IrDA SIR ENDENC up to 115.2K bpps
• Programmable DMA Channel can be assigned to
  service UART0 and UART1

53
Two I2C with DMA

• Each interface can be either Master or Slave
• Programmable clocks with support for various
  rates up to I2C Standard (100KHz) and Fast Rate
  (400KHz)
• Multi-master capability while in slave mode
• 7-bit or 10-bit addressing
• DMA Channel can be assigned to service each I2C
  Channel

54
Two Synchronous Serial Port (SSP) with DMA

• Each SSP interface supports
• SPI and similar synchronous serial interfaces SSI
  and Microwire
• Full duplex, three or four wire synchronous
  transfers
• Master or Slave operation
• Programmable clock bit rate up to 24MHz master,
  6MHz slave
• Separate transmit and receive FIFOs
• Programmable data frame size
• Programmable clock and phase polarity
• Specifically for Microwire
• Half-duplex transfers using 8-bit control
• Specifically for SSI
• Full duplex four wire synchronous transfers
• Transmit pin tri-stateable when not transmitting
• A DMA channel may be assigned to service each SSP
  channel

55
EMI Specifics (128 and 144 pin pkgs)

• Supports static asynchronous memory cycles
• 16-bit multiplexed data, 8-bit multiplexed data
  and 8-bit non-multiplexed data modes
• Configurable memory region each with Chip Select
• Programmable wait states per memory region
• 16-bit multiplexed data mode options
• 3 configurable memory regions each with up
  24-bit address range
• 4 configurable memory regions each with up to
  23-bit address range
• 8-bit multiplexed data mode options
• Most efficient for 3 configurable memory regions
  each with 8-bit address and 8-bit data
• Can be configured with external latch for 3
  configurable memory regions each with up to
  24-bit address range
• 8-bit non-multiplexed mode
• 3 configurable memory regions each with up to
  16-bit address range

56
Burst Mode EMI Specifics (144 pin pkg)

• Support for Asynchronous (burst) memories
• BGA144 packaged STR91X devices will support
• Direct connection to Pseudo SRAM (PSRAM)
• Connection to Burst Flash Memory
• More info coming on connection details

57
STR9 Int vs. Ext Memory Performance Instr

• Assumptions
• 32-bit Instructions, 1 cycle to execute each
  instruction
• Memory wait states is set at 4 for asynchronous
  accesses
• Code has 80 sequential addresses, 20
  non-sequential (branches)

This means the CPU can execute code 5.3 times
faster when stored in internal Flash memory
compared to being stored in external Flash memory
58
STR9 Int vs. Ext Memory Performance Data

• Assumptions
• 32-bit Data
• Data access is 80 sequential addresses, 20
  non-sequential (random)

This means the CPU can access data 13.3 times
faster when stored in internal SRAM compared to
being stored in external SRAM
59
Timer Specifics

• Four independent timer counters featuring
• 16-bit free running timer/counter
• Clock source from programmable 16-bit pre-scale
  of CPU Clk
• Optional external clock
• Two 16-bit capture registers for measuring two
  input signals
• Two 16-bit output compare registers for
  generation of two output signals
• PWM Output with 16-bit resolution on both
  frequency and width
• Pulse generation in response to external event
• Dedicated CPU interrupt with 5 flags
• DMA Channel can assigned to each of TIM0 and TIM1

60
GPIO

• 128-pin and 144-pin packages
• 80 GPIO (10 I/O ports)
• 80-pin package
• 40 GPIO (6 I/O ports)
• 16 GPIO have higher current (4mA source, 8mA
  sink)
• All GPIO default to high impedance input mode,
  with some GPIO additionally routed to certain
  peripheral inputs
• CPU firmware initializes GPIO pin functionality
  through switch matrix
• Bit masking available on each port, no
  Read-Modify-Write needed
• 12 MHz maximum GPIO pin toggling from firmware,
  CPU at 96 MHz
• All GPIO 5V tolerant
• There are no internal pull up or pull down
  resistors recommended to ground all unused GPIO
  pins

61
Voltage Sources
128 and 144 PIN DEVICES
80 PIN DEVICES
AVREF_AVDD
OPTIONAL 1.0V to AVDDQ
AVREF
A/D Converter
A/D Converter
AVDD
OPTIONAL SOURCE
AVSS_VSSQ
AVSS
D
A
3.0 or 3.3V VREG
3.0 or 3.3V VREG
VDDQ
VDDQ
I/O RING and FLASH
I/O RING and FLASH
VSSQ
VSSQ
D
D
VBATT
VBATT
BATTERY or SUPERCAP
BATTERY or SUPERCAP
RTC
RTC
SRAM
SRAM
OPTIONAL
OPTIONAL
VDD
1.8V VREG
VDD
1.8V VREG
ARM9E CORE
ARM9E CORE
VSS
VSS
D
D
62
CAPS- Configuration and Programming Software for
PC

• Assistance to select individual pin functions
• Configure clock sources and frequencies
• CAPS generates report to document your design
• CAPS generates a header file which reflects your
  choices
• Header file is compatible with ST Firmware Library

63
CAPS Pin Configuration
64
Thank You