A SIMPLE DSP PROCESSOR

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A SIMPLE DSP PROCESSOR
JAYRAM K. MURALI
MOHAN SATYA KIRAN B. AMARENDER REDDY
SUDHANSHU VINOD KUMAR BANSAL
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Whats NEW in our work?
Implementation of Instruction Set based on Area
and hence Architecture Limitations
Bi directional Carry propagate BIT REVERSER for
specified number of bits
Complete Code preparation for FFT Implemention
with our Instruction set
Place and route the netlist generated by
synopsys using L-Edit.
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SALIENT FEATURES

• 6T Cell Register Array
• 11 General Purpose Registers
• Twin Accumulator Organization
• Auto Post increment (decided by Increment Flag)
• Shift decision flags
• Single Instruction Looping
• Bit Reverse Instruction
• Addition of 8 bit number to 16 bit number
• Register Indirect Addressing
• PC relative branching
• Stack Pointer

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Basic Architecture
DATA PORT
DATA BUF
DATA BUS
IR
TR1
TR2
BUS MUX
SHIFTER
Bit Rev
ALU
MAC
CNTRL LOGIC
R0 R1
STATUS REG
ADDRESS BUS
R2 R3
R4 R5
R6 R7
STATE REG
MAR
R8 R9
MA XX
ADDRESS PORT
INCR
SP
PC
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Part B
OVERVIEW OF INSTRUCTION SET
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CLASSIFICATON ON THE BASIS OF
FUNCTIONALITY

1. DATA TRANSFER 2. ARITHMETIC 3.
LOGICAL 4. BRANCHING 5. CONTROL
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1. DATA TRANSFER A. MOV Rd , Rs
Rs,Rd ? R0 - R9/MA/SPH/SPL/XX
( 16 bit INSTRUCTION )
B. MOV Rd , M Rs ? R0 - R9/ MA/XX,
M ? M1/M2
M1 R6R7 M2 R8R9 C.
PUSH Rd Rd ? R0 - R9/PCH/PCL/MA
/ POP D. MVI Rd , 8bit data Rd ?
R0 - R9/MA/SPH/SPL/XX
( 16 bit INSTRUCTION )
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2. ARITHMETIC A. ADDM/SUBM Rd , M1/M2
Rd ? R0 - R5 B. MAC Rs1,Rs2
Rs1,Rs2 ? R0 -R5/M1/M2 B. MUL
Rs1,Rs2 Rs1,Rs2 ? R0
-R5/M1/M2 C. INC/DCR R
R ? R0 - R9 D. INX/DCX Rp
Rp ?R6R7/R8R9,SP
E. CMP Rd/Rs
Rd ,Rs ? R0 - R5 F. ADD/SUB R1/R2, R
R ? R0-R5 G. ADDL Rp, R
Rp lt R4R5 R
Rp ? R6R7, R8R9 R?R0-R3
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3. LOGICAL A. CM R (complement )
R ? R0 - R3 B. SO/SA 8 bit data
(SR OR /AND ) C. SH R
R ? R0 - R5
D. BR Rd, Rc Rd ?
R0,R1 Rc ? R2,R3 E. XOR/OR/AND R
R ? R0 - R5
(R1 lt-- R1 op R)

- nature of shift arithmetic/logical and
left/right is decided by status register
setting. BR- Bit Reverse, SR status Register,
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4. BRANCHING A. JMP Rp Rp
?R6R7/R8R9/R4R5 -- register direct B.
JMP 8 bit data -- PC relative jump C.
JNZ/JC Rp Rp ?R6R7/R8R9/R4R5 D. JNZ/JC 8
bit data -- PC relative conditional jump
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5. CONTROL A. RPT R
R ? R0 - R3/ XX -- repeat instruction
for -- single inst hardware looping B.
HLT C. NOP
Total Instruction types 29
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Off Line FIR Impelmentation
MVI SPH, -- MVI SPL, -- MVI R4,
IPADH MVI R5, IPADL SO 01H
to set post increment mode on MVI
R2, 00 MVI R6, OPADSH MVI R7,
OPADSL PUSH R6 PUSH R7 ADDL R6R7, R2 MVI
R3, 10H assuming 16th
order MVI R8, COEFFADSH MVI R9,
COEFFADSL MVI MA, 00 RPT R3 MAC
M1,M2 POP R7 POP R6 MOV M1, MA INC
R2 CMP R0, R2 JNZ L1 HLT
L1
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On Line FIR Implementation
MVI R8, OPADSH MVI R9, OPADSL MVI SPH,
-- MVI SPL, -- PUSH R8 PUSH R9 MVI R6,
DLSH MVI R7, DLSL PUSH R6 PUSH R7 MVI
R4, DLEH MVI R5, DLEL MVI R3, 10H MVI
MA,00 MVI R8, COEFFADSH MVI R9,
COEFFADSL MAC M1, M2 DCR R3 JNZ L1 INX
R8R9 MOV R0, M2 MVI R8, OIPADH MVI R9,
OIPADL MOV R1, M2
MAC R0, R1 MOV M1, R1 POP R9 POP
R8 MOV M2, MA INX R8R9 PUSH R8 PUSH
R9 INX SP INX SP JMP L3 INX
R6R7 INX R8R9 CMP R4R5, R6R7 JNZ
L2 POP R7 POP R6 JMP L2
L3
L1
L2
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IMPLEMENTATION OF N POINT RADIX-2 FFT
MVI R2 ,01 MVI R3 ,01 MVI R1 ,V SUB
R1,R2 PUSH R1 PUSH R3 PUSH R1 PUSH R2 MVI
XX,04 RPT XX INX SP MVI R0,FF MVI R2,00 BR
R0,R2 MOV XX,R0 BR R0,R2 PUSH R2 INX SP RPT R1 SH
R2 POP R5 POP R4 ADDL M1,R2 MOV R1,M1 POP R5
POP R4 ADDL M1,R2 MOV R3,M1 POP R5 POP R4 ADDL
M1,R0 MUL M1,R3 MOV R2,MA MUL M1,R1 POP R5 POP
R4 ADDL M1,R0 MAC R3,M1 MOV R3,MA MUL M1,R1 MOV
R1,MA SUB R1,R2 ADDL M1,XX MOV R8,R1 MOV
R2,M1 ADD R1,R2 MOV M1,R1 MOV R1,R2 MOV R2,R8
L5
L3
L1
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SUB R1,R2 ADDL M1,R0 MOV M1,R1 DCX SP DCX SP DCX
SP DCX SP POP R5 POP R4 ADDL M1,XX MOV R1,M1 ADD
R1,R3 MOV R2,M1 MOV M1,R1 MOV R1,R2 SUB
R1,R3 ADDL M1.R0 MOV M1,R1 MVI XX,09 RPT XX DCX
SP POP R3 POP R1 DCR R1 POP R2
CMP R1,R2 JZ L2 INR R2 MOV R1,R3 JMP L1 MVI
R1,N-1 CMP R0,R1 JNZ L3 DCX SP DCX SP DCX SP DCX
SP POP R2 MVI R1,V CMP R1,R2 JNZ L4 HLT INR
R2 INX SP POPR3 SH R3 INX SP JMP L5

L2
L4
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Off Line FIR 24 Instructions
40 bytes On Line FIR
42 Instructions 64 bytes
FFT Implementation

• In Place Computation
• Radix-2 Implementation
• Generalized upto 256 point FFT
• 97 instructions
• uses a program memory of 130 bytes
• Input is assumed to be complex, hence can be
  used for IDFT

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Pin Configurations
Total Pins 40 Used Pins 35
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ESTIMATION
Area for routing 36 or 1 mm2
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S-EDIT LAYOUT OF A 8 BIT ALU
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(No Transcript)
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Bidirectional Carry - Bit Reversing Counter for
FFT
Performs Bit Reversal for Required number of bits
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FLOORPLAN
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OPEN FOR COMMENTS