Title: SoftwareDefined Radio Project
1Nan Zhou, Berkeley Wireless Research Center Niko
Brüls, Infineon Technologies
Software-Defined Radio Project Prototype Design
on BEE-Platform
N e v e r s t o p t h i n k i n g .
2Outline
- Introdution to Software Defined Radio
- Motivation / Goals
- HW Architecture Overview
- Implementation on the BEE
- First Implementation Step
- Using the BEE Tool Flow
- Future directions
3Trend in Digital Baseband Processing
Flexibility
Relative Power
Acc Accelerator DSP Digital Signal Processor
Mem Memory rDPU Reconfigurable Data
Processing Unit CU Control Unit L1 Layer-1
Control PHY Physical Layer SIMD
Single Instruction Multiple Data
4SDR Project Goals
- Multiple-core DSP platform with the following
specification - Easy-to-program and flexible solution within
power budget - Digital baseband architecture for these standards
- UMTS FDD at 384 kb/s
- CDMA2000 1x DV
- GSM/GPRS/EDGE class 12
- IEEE 802.11b
- IEEE 802.11g (at reduced data rate, e.g. 24 Mb/s)
- Bluetooth
- DAB
- GPS
- SIMD DSP core verified on FPGA and implemented in
90nm technology
5Multiple DSP Core Platform
Baseband Processing
SIMD Core Cluster
GPCore (L1 Control)
ARMCore (MAC)
RFInterface
BusBridge
I DCache
I DCache
Accel.
Accel.
Memory
Shared Memory
Peripherals
a b c
Turbo/Viterbi Dec.
FIR Filter
96 K
96 K
96 K
96 K
xx K
6Why do prototyping in the BEE Environment?
- FPGA Emulation on BEE provides the speedup
necessary to verify the architecture as well as
the software running on it. - Common design environment for both FPGA ASIC
designs. - Matlab/Simulink is ideal for DSP oriented design
and simulation - BEE provides the capacity needed to emulate large
designs spanning multiple FPGAs.
7SIMD Core
Baseband Processing
SIMD Core Cluster
GPCore (L1 Control)
ARMCore (MAC)
RFInterface
BusBridge
I DCache
I DCache
Accel.
Accel.
Memory
Shared Memory
Peripherals
a b c
Turbo/Viterbi Dec.
FIR Filter
96 K
96 K
96 K
96 K
xx K
8SIMD DSP Core
- Each SIMD instruction operates on 4 x 32b data
- General Purpose Processor
- Used as controller for the SIMD array
- Can be C-Slowed 8 times to execute 8 threads
needed by the PE array
9SIMD DSP Core
Multi-Layer System Bus
10SIMD DSP Core
- Each SIMD instruction operates on 4 x 32b data
- General Purpose Processor
- Used as controller for the SIMD array
- Can be C-Slowed 8 times to execute 8 threads
needed by the PE array - Processing Element (PE) Array
- 4 PEs per SIMD Core
- Pipelined to 8 stages
- Combined data level and thread level parallelism
eliminates all pipeline dependencies.
11SIMD DSP Core
Multi-Layer System Bus
12Implementing the SIMD Core
- Simulink used as a unified design entry tool for
both ASIC and FPGA - PE array will be the same design for both ASIC
and FPGA - Difference between FPGA and ASIC implementation
- Multiple Micro Blaze Core used as SIMD unit
controller for FPGA design - Multi-threaded ARM Core will be used as the SIMD
controller for ASIC design - Common controller to PE interface so that Micro
Blaze and ARM can used interchangeably.
13First SDR prototype on a single FPGA (1/4 SIMD
core)
task 0 controller
128
we_0
I-cache
full_0
we_n
data
BRAM
full_n
fifo-if
PE- controller
data
re_0
opb-if
empty_0
task 0 programs data
data_0
32
128
ext. FGPA memory
Load/Store
re_n
empty_n
data_n
simplesharedmemory
opb-bus arbiter (data)
data
PE- data path
BRAM
1st arbitration stage mem if - serializer
local memory
task 1 programs data
128
we_0
Load/Store
full_0
Sync BRAM
opb-if
we_n
.BRAM-if
full_n
fifo-if
data
PE- controller
re_0
empty_0
data_0
Microblaze Subsystem
128
re_n
I-cache
empty_n
data_n
FPGA
task 1 controller
14Tool Flow
Matlab/Simulink Design Environment
15SDR prototyping on BEE Next Step
¼ SIMD Core
MB
FIFOs
PE
MB
- Not really a step toward higher level of system
integration - Heavy inter-FPGA communication
- New synchronization scheme required
16SDR prototyping on BEE Next Step
SIMD core 1
SIMD core 2
SIMD core 3
SIMD core 4
¼ SIMD Core
MB
FIFOs
PE
MB
- Includes all relevant system components
- Moderate inter-FPGA communication
17Thank You