Pyxis

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Pyxis

• April Lewis
• Aaron Martin
• Steve Sherk

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Pyxis1600

• General-purpose 16-bit RISC microprocessor
• 16 16-bit registers
• 16-bit address bus
• Up to 64KB of addressable memory

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Registers

• 16 registers
• 3 special purpose
• r0 zero
• r14 stack pointer
• r15 return address
• 13 general purpose
• r1 - r13
• Status register (sr)
• 8 bits carry (c), overflow (o), negative (n),
  zero (z), interrupt enable (i), less than (l), 2
  bits unused
• Program counter (pc)
• Accumulator high (ah) and accumulator low (al)
• Used for multiply and divide
• Interrupt Return Address (IRA)
• Register to hold return address from interrupt

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Instruction Formats
0
3
15
4
7
8
9
R-type
opcode
rd
rs
ext
0
15
Displacement / Immediate
0
8
9
12
13
15
opcode
branch type
address
B-type

• 16-bit instructions
• 7-bit opcode
• 1 bit to indicate information in next word
• rd is source and target
• rs is source
• Branch instructions use special format

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Instruction Set
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Instruction Set
Assembly to Machine Code Example
add r3, r4 comp r10, r4 beq 25 jmpr r9
0000001 0 0011 0100 1111111 1 1010 0100 1110000 x
xxxx xxxx 0000 0000 0001 1001 010xxxx x 1001 0000
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Addressing Modes

• Register direct
• Register indirect plus displacement
• Use r0 for absolute addressing
• PC-relative
• Immediate

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Datapath
9
Control Signals
10
Control Signals
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State Transition Diagram
0
Fetch
1
IorD0 MemRead1 MemWrite0 ALUOpADD ALUSrcA2 AL
USrcB2 PCSrc0 PCWrite1 RegWrite0
Decode
R-type (ext1)
Fetch Immediate
4
R-type (ext0)
2
Execute
Calc EA
Calc EA or Immediate
8
Write-back ALU to Reg
3
5
Memory Write
Memory Read
9
6
To State 0
Write-back Mem to Reg
15
7
Check Interrupt
12
State Transition Diagram
Fetch
Decode
0
1
R-type Jump Link
R-type Jump (ext1)
R-type Jump (ext0)
B-type
Save Return Addr
13
Jump to Reg Addr
Compare
10
12
14
Jump
11
Update PC
To State 15
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Interrupts

• Interrupts will be checked at the completion of
  each instruction
• An interrupt will trigger some extra states that
  send the processor to an Interrupt Service
  Routine (ISR), pre-programmed in code memory.
• These states will perform the following
• Save the processors state
• Disable interrupts
• Jump to the ISR
• The RETI instruction will return the processor
  from the ISR

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Virtex XCV300 FPGA

• XCV300 FPGA
• - 322,970 logic gates
• - 8 KB on-chip RAM
• - Block SelectRAM
• - Fast arithmetic carry
• - Clock Speed 10MHZ
• - Multiple I/O standards (LVTTL, LVCOMS2)

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Input / Output Serial Interface

• UART Transmitter and Receiver Macros

UART_TX
UART_RX
8-bit
Serial
Serial
16 Byte FIFO BUFFER
8-bit
16 Byte FIFO BUFFER
These macros are fully compatible with standard
UART communications protocols such as to a PC,
providing level shifting components are employed
to generate RS232 signaling. The buffers will be
interrupt driven.
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Memory Timing Diagrams

• 32KB FLASH (AT29C256-70PC)

Total access time is 70ns (tACC)
70ns
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Memory Timing Diagrams

• 32KB SRAM (K6x0808C1D-DF70)

Total access time is 70ns (tAA)
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32KBx8 off-chip SRAM32KBx8 off-chip FLASH
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Parts List
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Roles and Responsibilities

• Aaron
• Logic design
• Verilog programming
• Hardware implementation
• April
• Logic design
• Verilog programming
• Assembler
• Steve
• Logic design
• Verilog programming
• Hardware implementation
• All
• Test programs
• Integration and Test
• Documentation

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Schedule
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Questions