Architectures de processeurs volus

1
Implementation of Image Processing onto FPGA
using modular DSP C6201 VHDL model
Pr. Michel Paindavoine
University of Burgundy Le2i UMR CNRS 5158
Dijon, France

2
Context
Omnipresence of the electronic systems
Million transistors per head
1000
PDA Mobiles MP3 player
500
1995
2000
2005
2008
3
Context
Market strong constraints
Performances
Design
Increasing functionalities
Quick (Time To Market)
Processing capability in rise
Internet
Evolutionary step
Consumption in fall
Low cost
Dimension in fall
4
Context
Silicon technology progress
Technology in nm
200
100
50
2005
2010
2000
Integration capacity 100 every 2 years
(Moores law)
transistor cost drop by 40/year
Clock frequency 100 every 3 years
5
Context
Limiting factor propagation time
Propagation time in ps
Total
40
30
connections
20
10
Internal
100
650
350
180
Technology in nm
Pentium internal frequency at 3 GHz but external
communication lt 500 MHz
Decrease the component number
6
Context
Design
10,000
100,000
1,000
10,000
100
1000
Gap
IC capacity
10
100
Transistors par puce (en millions)
1
10
0.1
1
Productivity (K)Transistors per head-Month.
Design productivity
0.01
0.1
0.001
0.01
1981
1983
1985
1987
1989
1991
1993
1995
1997
1999
2001
2003
2005
2007
2009
To reuse the design
To improve the design methods performances
7
Context
Design reuse
SIA Roadmap gt 90 of reuse
8
Context
Electronic system
Heterogeneous hardware architecture
Software
SoC (System on Chip)
General purpose processor
Specific processor (DSP)
Specific logic bloc
Interfaces I/O
Memory
9
Context
Component dematerialization
process(clk) begin if rising_edge(clk) then a lt
1 end if end process
Hardware library
Physical components
Virtual components
Processors
Processors cores
Components sale
Intelectual property (IP) sale
10
Context
Need co-design tools
System specification
HW/SWPartitioning , Communication synthesis
Performance analysis / co-simulation CPU time,
memory size, consumption, bus activity
NON
Goal achieved ?
Synthesis tools
RTL ASIC / FPGA
C, asm DSP, microcontroler
Interface
11
Context
SoC
ASIC (Application Specific Integrated Circuit)
FPGA (Field Programmable Gate Array)
Reconfigurability(ms) Rapid prototyping More
comsumption than the ASIC
Not adapted to the evolution Design and test
expensive
12
Context
Domain Rapid prototyping for Image processing
Environment SoC design
VHDL
Goal To generate optimized DSP cores

• Constraints
• Methods proposed
• compatible with existing tools
• for not-expert in electronic

13

• Target processor choice

• Target processor choice

• The design flow proposed

• Experimental validations

• SynDEx interface

• Conclusion and perspectives

14
Target processor

• Image processor

• To use an existing DSP as model

• 2 architectures

• superscalar

• VLIW (Very Long Instruction Word)

14
15
Target processor
Superscalar
main(void) int a,b for (a0alt 10a)
bb5
VLIW
Standard compiler
VLIW compiler
I1 I2 I3 . .
I1 I2 I3 I4 I5
Instructions repatition unit
. . .
UC 1
UC 2
UC n
Interconnections
Data memory
. . .
R1
R2
R3
Rn
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DSP
16
Target processor
Target processor DSP TMS320 C6201
VLIW architecture simplification of VHDL model
TI documentation and librairies
Optimal programming work available
Self expérience in LE2I
16
17
Target processor
C6201 architecture
186 Instructions
Instruction address
Instructions memory
D1
Instruction
D2
Data address
L1
Data memory
Data
L2
M1
A0
B0
M2
A1
B1
S1
A2
B2
S2
A15
B15
calculating units
Registers
17
18

• Target processor choice

• The design flow proposed

• The design flow proposed

• Experimental validations

• SynDEx interface

• Conclusion and perspectives

18
19
Design flow
Soft processor core is frequently use in SoC
Goal to generate a harware model just for an
application
Instruction set
DSP
I1
main(void) int a,b for (a0alt 10a)
bb5
I2
Registers
I3
R1
R2
R3
R4
I4
Compiler
I5
Calculating units
I6
UC 1
UC 2
I7
Instruction 2, 4, 7 and 8
R1 and R3
UC 1
I8
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20
Design flow
Source writing in C or C6201 assembler
Automatic processor VHDL model generation
Automatic hardware characteristics extraction
Soft fonctionnel simulation
Synthesis Routing
Hardware Database
C6201 Code
FPGA bistream
20