NOCARC Network on Chip Architecture

1
NOCARCNetwork on Chip Architecture

• Axel Jantsch
• Royal Institute of Technology
• Stockholm

2
Outline

• NoC Architecture overview
• Activities
• Switch Design
• Buffer-less
• Hot-potato routing
• Stress sensitive routing

3
NoC Architecture Overview
Switch
Resource

• Message passing communication infrastructure
• Physical-Architectural Level design integration

4
Resource-Network Interface
RNI
Resource
5
Concept of Region

• Resources larger than a slot
• FPGA
• Memory
• Parallel processor
• Wrapper will make the region transparent to
  outside traffic
• Communication within a region could happen
  differently than rest of the network

Wrapper
6
Quick Summary of Activities

• NoC Architecture Implementation
• Physical feasibility study
• Buffer Less Switch Design
• NoC Evaluation
• Ns-2 based NoC Simulator
• Dedicated simulator for NoC
• Nostrum protocol stack
• 5-layered protocol stack
• Two Phase Design Methodology
• Special Purpose NoC Region
• NoC Specific Fault Model and Error Protection
• NoC Specific Quasi-synchronous Clocking

7
Buffer Less Switch
Packet
Packet
Packet
Switch
Packet
Packet
Packet
Packet
Packet
8
Load distribution using Stress values

• Load information sent between switches, stress
  value
• no Stress value
• with Stress value
• averaged Stress value (four cycles)
• Better routing decisions for intermediate load
• Larger design

9
Final implementation
10
Results of synthesis
(using Synopsys)
11
Maximum probability for various mesh sizes
12
Network delay
13
Number of packets in centre FIFO
p0.47
p0.48
p0.49
p0.50
14
Average load in FIFOs with no Stress value
max3.2
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Average load in FIFOs using Stress value
max0.9
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Average load in FIFOs using averaged Stress value
max0.15
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Comparing results
max0.9
max0.15
max3.2
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Conclusion

• A buffer-less switch is feasible
• Very low cost and high performance
• Stress values is a simple control mechanism
• It increases maximum load by 20
• It decreases the maximum latency by factor of 20
• www.ele.kth.se/NOC