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Decided to order a production run instead of another proto-type run ... DORIC sepc: 10-11. Opto-link error rate is limited by SEU ...
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Opto-board #1 Data Optical Power. Anneal at Iset of 1.5 mA and all high ... Anneal at Iset of 1.5 mA and all high. Irradiate at Iest of 0.6 mA and PRBS ...
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X-section. Opto-board. SMT caps. PP0. New heat spreader. M1.5 screw. grease ... Top view. optoboard. Smt cap. Thermal bridge. New heat spreader ...
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Incoming data stream is sampled and digitised in the back-of-crate cards (Main) free parameters: Sampling point (Rx delay) Threshold 0/1 ...
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... pixel racks already ... allocate max 16 BOCs, 4 crates are needed, 2 racks (7% spare) ... (There are free racks close to the pixel rack: it should be perfect) ...
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pixels were masked as too hot in a source scan in self triggering mode. ... we had a failure in Wiener PS for ROD crates) 17. Shift Training. Typical steps. ...
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Very similar behaviour for all local supports (L0/L1/discs). Full loop power ... Disk top modules increased their temp of less than 2C ...
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US ATLAS Pixel Meeting July 18-19, 2002 UC Santa Cruz Meeting Agenda Overall Cost increases in a number of areas were identified and a few cost decreases.
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VDC, DORIC and opto-package (VCSEL and PiN) PiN photodiode is most ... 'SEU' is depending on signal size in the photodiode -- independent of DORIC Version ...
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... testing setup is tolerable for TLK2501 transceivers operating at 80.00 Mhz using ... One set of TTCvi and TTCvx modules is being used for CCB testing at Rice ...
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ToT: width of the discriminator output signal proportional to the deposited ... ToT measurement of crossing particles (Pixel only) Hits/Clusters properties ...
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ID status ATLAS week June 2004
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Mezzanine Card pin assignment done. A24D16 VME Interface based on glue logic (address ... (main 9U board Altera-based mezzanine card) have been fabricated so ...
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1.0 BX input latching @ 80MHz and multiplexing with FIFO - 1.5 BX sorting '3 out of 18' ... latches, data buffers, comparators, DS/DTACK logic, CSR0) CCB ...
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